Sequential Logic ICs
Sequential logic contains memory. Its output can depend on both present inputs and previous state.
Latch
A latch stores one bit while an enable condition controls when the input may change the stored state.
Flip-flop
A flip-flop normally changes state in response to a clock edge. Common forms include D, JK, and T flip-flops.
D flip-flop
The D flip-flop captures its D input on the active clock edge and holds that value at Q until the next qualifying event.
The 74x74 family is a familiar dual D-type edge-triggered flip-flop with asynchronous preset and clear.
JK flip-flop
The JK form expands the older SR idea so the state can be set, reset, held, or toggled depending on J and K.
Counters
Counters advance through a sequence of states. They can divide frequency, count events, scan displays, create timing sequences, and address memory.
| Counter style | Characteristic |
|---|---|
| Ripple / asynchronous | Each stage clocks the next; simple but cumulative delay occurs. |
| Synchronous | All stages share the clock; internal logic decides which bits change. |
| Up/down | Can count in either direction. |
| Decade / BCD | Cycles through ten states rather than all binary combinations. |
| Johnson / ring | Shift-register-derived sequences useful for scanning and timing. |
Shift registers
A shift register moves stored bits from one stage to another on each clock. Versions provide serial-in/parallel-out, parallel-in/serial-out, and bidirectional operation.
Registers and latches
Parallel registers store several bits at once. Octal latches and flip-flops are common for holding bus data and controlling outputs.
Clock quality matters
A clock input should have clean transitions and satisfy minimum pulse-width, rise/fall-time, setup, and hold requirements. A slowly bouncing mechanical switch is usually a poor clock source without debouncing.
Setup and hold time
Data must normally be stable for some interval before and after the active clock edge. Violating these requirements can cause uncertain or metastable behavior.
Asynchronous controls
Preset, clear, reset, or set inputs can change state without waiting for the clock. They are useful but can create difficult timing problems if released at the wrong moment.