CMOS — Complementary MOS Logic
CMOS uses complementary N-channel and P-channel MOSFETs. A basic CMOS gate is arranged so that one transistor network pulls the output toward the positive supply while the complementary network pulls it toward ground.
The CMOS inverter
A simple inverter uses one P-channel MOSFET above one N-channel MOSFET:
- Input LOW: P-channel device on, N-channel device off, output HIGH.
- Input HIGH: P-channel device off, N-channel device on, output LOW.
Ideally, in either steady state one transistor is off, so there is no direct DC path from supply to ground.
Very low static power
This complementary action gives CMOS its famous low static power consumption. Real devices still have leakage, and modern dense processors can have significant leakage, but classic CMOS logic consumes most of its dynamic power while charging and discharging capacitances during switching.
- α — activity factor.
- C — switched capacitance.
- V — supply voltage.
- f — switching frequency.
The V-squared term is one reason modern processors operate at much lower supply voltages than early 5 V logic.
CMOS input current
The insulated MOS gate draws very little steady DC current. However, each input has capacitance, and the driver must charge or discharge that capacitance during a transition.
Floating CMOS inputs
4000-series CMOS
The CD4000 family made CMOS logic widely available in the 1970s. Many devices operate over a broad supply-voltage range and have excellent noise margins, but original 4000-series parts are much slower than many modern CMOS families.
74HC
74HC provides classic 7400-series functions using high-speed CMOS technology. Its input thresholds are CMOS-like rather than traditional TTL-like.
74HCT
74HCT uses CMOS internal construction but has input thresholds designed to be compatible with traditional TTL output levels at a 5 V supply. It is a useful bridge between old TTL systems and CMOS logic.
Other CMOS families
Modern catalogs contain many additional families such as 74AC, 74ACT, 74LVC, 74AUC, and others, optimized for different voltage, speed, drive, and power requirements.
Latch-up
Traditional bulk CMOS structures contain parasitic transistor paths that can form an unintended silicon-controlled-rectifier structure. Under severe input or supply conditions this can latch into a high-current state. Modern processes greatly reduce susceptibility, but absolute maximum input limits still matter.
ESD sensitivity
The thin MOS gate dielectric can be damaged by electrostatic discharge. Integrated protection structures improve robustness, but normal ESD handling is still appropriate.