LearnTronics
The D Flip-Flop and Timing
The D flip-flop stores one bit at a clock edge
The D flip-flop is one of the most useful memory elements in digital electronics.
The simple logical idea
At the selected clock edge:
Between active clock edges, Q holds its stored value.
Three timing specifications now matter
Setup time: D must become stable a certain time before the active clock edge.
Hold time: D must remain stable for a certain time after the edge.
Clock-to-Q propagation delay: Q changes a little after the clock edge.
This is where “delay” stops being optional knowledge
Boolean algebra tells us what value should be stored. Timing specifications tell us whether the physical flip-flop had enough time to recognize that value reliably.
Violating setup or hold time
If the data changes too close to the sampling edge, the device can enter a temporary uncertain condition called metastability. Designers therefore treat setup, hold, clock frequency, and propagation delay as real engineering limits, not merely theoretical details.
From one bit to registers and counters
Several flip-flops can store several bits. Arranged in groups they form registers; connected with appropriate feedback they can form counters, shift registers, state machines, and many other digital systems.